The present invention relates to a semiconductor device in which transistors different in applied voltage from one another are embedded, and a method of manufacturing the same.
An increase in gate leakage current in silicon oxide system gate insulating film, and depletion in a polysilicon system gate electrode have become problems with promotion of high integration of MISFETs. As measures taken to cope with such problems, adoption of a gate stack structure having a gate insulating film having a higher permittivity larger than that of a silicon oxide, and a metallic gate (hereinafter referred to as “a high permittivity film/metallic gate”) is discussed for high-speed operation and low-power consumption MIS type transistors. However, utilizing a normal manufacturing method results in that a heat history after the high permittivity film/metallic gate is formed is high. As a result, there is encountered such a problem that the characteristics and reliability of the high-permittivity insulating film are deteriorated, and a value of a work function of the metallic gate shifts from a design value.
In order to solve this problem, a buried gate (for example, a damascene gate) structure is proposed. This buried gate structure is obtained by completing a prime heat treatment process necessary for transistor formation before the high permittivity film/metallic gate is formed. The technique relating to this buried gate structure, for example, is described in Japanese Patent Laid-Open No. 2001-102443 (hereinafter referred to as Patent Document 1). A method of forming this buried gate structure when a metallic electrode, for example, is used is described as follows. That is to say, a gate insulating film and a gate electrode portion are removed once after a transistor structure having a silicon oxide system gate insulating film and a polysilicon system gate electrode is formed, and a metallic system oxide film and a metallic electrode are newly buried therein. According to this method, the metallic electrode is prevented from being deteriorated because the heat treatment necessary for the transistor formation is completed before the formation of the metallic electrode.
However, the high-speed operation and the low-power consumption are demanded for the actual semiconductor devices. For this reason, in order to meet these requirements, a transistor adopting the metallic system oxide film and the metallic electrode, and a transistor adopting an existing silicon oxide system gate insulating film and the polysilicon system gate electrode for the high-speed operation are mixedly formed in the actual semiconductor device. Therefore, the damascene gate structure having the high permittivity film/metallic gate for the high-speed operation and low-voltage operation, and a gate structure having a thicker gate insulating film showing a high withstand voltage have to be formed on the same semiconductor substrate of the same chip in the embedded manner.
Patent Document 1 discloses a method of manufacturing a transistor structure having a polysilicon gate electrode made of cobalt silicide and a gate insulating film formed from a silicon oxide film, and a damascene structure having a titanium nitride film and a tantalum oxide film. In addition, a method is also proposed in which a damascene gate electrode for a high-speed operation and low-voltage operation is formed to be higher than a polysilicon gate electrode for a high-withstand voltage operation in a damascene gate processing stage. Also, this method aims at preventing the polysilicon gate electrode from being polished when a metal is polished by utilizing a chemical mechanical polishing (CMP) method. This method, for example, is described in Japanese Patent Laid-Open No. 2004-6475 (hereinafter referred to as Patent Document 2).
In the case of the structure in which the low-voltage operation transistor (LV) having the damascene structure having the high-permittivity film/metallic gate for the high-speed and low-power consumption operation, and the high-withstand voltage (high-voltage operation) transistor (MV/HV) having the silicon oxide/polysilicon gate are integrated on one chip, it is disclosed to form a gate silicide layer of the high-withstand transistor before the formation of the low-voltage operation transistor. This, for example, is described in Patent Documents 1 and 2.
With the technique described in Patent Document 1, when a dummy polysilicon gate of the low-voltage operation transistor is removed, a cobalt silicide layer of the polysilicon gate of the high-withstand voltage transistor is used as a mask in order to prevent the polysilicon gate in the high-withstand voltage transistor region from being etched. However, there is still left such a problem that a gate resistance value increases because the cobalt silicide layer is trimmed.
On the other hand, as shown in the technique described in Patent Document 2, when an interlayer insulating film is polished by utilizing the CMP method, the central portion of the interlayer insulating film sags downward due to roughness and denseness of a density with which the gate is formed. As a result, there is caused such a problem that a metalized film formed by utilizing an electroless plating method is left in the resulting recess portion when the metallic film is subsequently polished by utilizing the CMP method. When the polishing is performed excessively for the purpose of preventing the metallic film from being left in the recess portion, the polysilicon gate is over-trimmed. In order to solve this problem, the method described in Patent Document 2 is proposed such that the damascene gate (replacement gate) of the low-voltage operation transistor is formed to be higher than the gate of the high-withstand voltage transistor in the stage of processing the dummy gate. However, it is not easy to suitably determine the processing conditions or the like for the dry etching of the dummy gate for the purpose of controlling a base step necessary for the lithography process in the phase of processing the dummy gate.